This application corresponds to Korean patent application No. 34764/1996 filed Aug. 21, 1996 in the name of Samsung Electronics Co., Ltd. which is herein incorporated by reference for all purposes.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a sub-wordline driver for transmitting an enable voltage to a wordline in response to an output signal of a main word decoder as a row decoder.
2. Description of the Related Art
A semiconductor memory device includes a memory cell array comprised of a plurality of memory cells connected between a plurality of wordlines and a plurality of bitline pairs, and peripheral circuits for inputting/outputting data stored in the memory cells. The respective addresses are designated to the wordlines and bitline pairs connected to the memory cells, respectively. Input addresses are decoded by a row decoder and a column decoder to select a specific wordline and bit line pair.
Particularly, a memory cell for a dynamic random access memory (DRAM) is composed of a transistor and a capacitor. The transistor is called an access transistor and the capacitor is called a storage capacitor. The capacitor is means for storing data, and the transistor is means for controlling the input/output of the data stored in the capacitor. The gate of the transistor is connected to a wordline, one end of the transistor is connected to a bitline, and the other end thereof is connected to one end of the capacitor.
When data of a logic "high" level is input/output to/from the capacitor of the memory cell, if a wordline enable voltage of a logic "high" level, i.e., an operating power supply voltage level, is applied to the wordline, a sufficient signal level might not be input/output to/from the capacitor of the memory cell due to a threshold voltage of the transistor. Therefore, it is common to supply a boosted voltage as the wordline enabling voltage to the wordline. A wordline driver is used to drive the boosted voltage.
Also, when the capacity of a semiconductor device is increased, the number of memory cells connected to a wordline is increased. As the wordline becomes longer, the load capacitance for the wordline is increased. Due to the increased load capacitance of the wordline, the speed loss becomes serious during enabling of the wordline, which impedes a high-speed access of the semiconductor memory device. To overcome this problem, the size of the wordline driver can be increased. However, it is quite difficult to increase the size of the circuits and elements in high-density integrated semiconductor devices. This is because the pitch between wordlines is shorter due to the small size in the design rule of the semiconductor memory device. Thus, it is very difficult to increase the size of the wordline driver.
Therefore, to solve the above-mentioned problems, the structure of a sub-wordline driver or split wordline driver (SWD) is adopted. However, the conventional semiconductor memory device having the sub-wordline driver structure must use a boosted voltage as the power supply voltage of the main word decoder. Accordingly, the boosted voltage is applied to a gate oxide film of a transistor constituting the main word decoder. The intensity of an electric field applied across the gate oxide film of the transistor is increased, which deteriorates the reliability of the gate oxide film.